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X80130, X80131, X80132, X80133, X80134
Data Sheet January 20, 2005 FN8152.0
PRELIMINARY
Voltage Supervisor/Sequencer
Triple Programmable Time Delay with Local/Remote Voltage Monitors
The X80130 is a voltage supervisor/sequencer with three built in voltage monitors. This allows the designer to monitor up to three voltages and sequence up to four events. Low voltage detection circuitry protects the system from power supply failure or "brown out" conditions, resetting the system and resequencing the voltages when any of the monitored inputs fall below the minimum threshold level. The RESET pin is active until all monitored voltages reach proper operating levels and stabilize for a selectable period of time. Five common low voltage combinations are available, however, Intersil's unique circuits allow any voltage monitor threshold to be reprogrammed for special needs or for applications requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. Activating the manual reset both controls the RESET output and resequences the supplies through control of the ViGDO pins. The X80130 has 2kb of EEPROM for system configuration, manufacturing or maintenance information. This memory is protected to prevent inadvertent changes to the contents.
Features
* Triple Voltage Monitor and Sequencing - Three independent voltage monitors - Three time delay circuits (in circuit programmable) - Remote delay via SMBus - Programmable voltage thresholds and delay times - Sequence up to 4 power supplies. * Fault Detection Register - Remote diagnostics of voltage fail event. * Debounced Manual Reset Input * Manufacturing/Configuration Memory - 2Kbits of EEPROM - 400kHz SMBus interface * Available Packages - 20-lead Quad No-Lead Frame (QFN - 5x5mm)
Applications
* * * * * * * * * * * * * * * * * General Purpose Timers Long Time Delay Generation Cycle Timers / Waveform Generation ON/OFF Delay Timers Supply Sequencing for Distributed Power Programmable Delay Event Sequencing Multiple DC-DC ON/OFF Sequencing Voltage Window Monitoring with Reset ON/OFF switches with Programmable Delay Voltage Supervisor with Programmable Output Delays Databus Power Sequencing 100ms to 5 secs Selectable Delay Switches ATE or Data Acquisition Timing Applications Datapath/Memory Timing Applications Data Pipeline Timing Applications Batch Timer/Sequencers Adjustable Duty Cycle Applications
Pinout
X80130/31/32/33/34
VCC VSS NC A0 MR 15 14 (5mm x 5mm) 13 12 11 6 7 8 9 10 A1
20 19 18 17 16 V4GDO V4MON V3GDO V3MON DNC 1 2 3 4 5 WP RESET V1GDO V1MON SCL
VCC
DNC
SDA
VP
Ordering Information
PART NUMBER X80130Q20I X80131Q20I X80132Q20I X80133Q20I X80134Q20I VTRIP1 4.5 4.5 3.0 3.0 3.0 VTRIP3 3.0 2.25 2.25 2.25 0.9 VTRIP4 2.25 0.9 1.7 0.9 0.9 PACKAGE QFN QFN QFN QFN QFN
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X80130, X80131, X80132, X80133, X80134 Block Diagram
RESET SDA VSS VCC MR POR RESET LOGIC AND DELAY CONTROL AND FAULT REGISTERS BUS INTERFACE SCL WP A0 A1
VP VMON LOGIC V1MON VREF1 V3MON VREF3 DELAY1 V4MON VREF4 DELAY3 DELAY4 OSC DIVIDER RESET 4 4
EEPROM 2kbits
VSS V1GDO
SELECT 0.1s 0.5s 1s 5s
V3GDO
V4GDO
DELAY CIRCUIT REPEATED 3 TIMES VSS VSS
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Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C ViMON pins (i = 1, 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V ViGDO pins (i = 1, 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V SDA, SCL, WP, A0, A1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V MR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V VP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications
SYMBOL DC CHARACTERISTICS VCC ICC VP IP (Note 3) ILI ILO VIL VIH VOL COUT (Note 1) VTRIP1
(Standard Settings) Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER
Supply Operating Range Supply Current EEPROM programming voltage Programming Current Input Leakage Current (MR) Output Leakage Current (V1GDO, V3GDO, V4GDO, RESET) Input LOW Voltage (MR) Input HIGH Voltage (MR) Output LOW Voltage (RESET, V1GDO, V3GDO, V4GDO) Output Capacitance (RESET, V1GDO, V3GDO, V4GDO) V1MON Trip Point Voltage (Range) X80130 X80131 X80132 X80133 X80134 IOL = 4.0mA VOUT = 0V VIL = GND to VCC fSCL = 0kHz
4.5 1.0 9
5.5 2.5 12 10 15 15
V mA V mA A A V V V pF V V V V V V V V V V V V
-0.5 VCC x 0.7
VCC x 0.3 5.5 0.4 8
2.20 4.45 4.45 2.95 2.95 2.95 0.85 4.50 4.50 3.00 3.00 3.00
4.70 4.55 4.55 3.05 3.05 3.05 3.5 3.00 2.25 2.25 2.25 0.90 3.05 2.30 2.30 2.30 0.95
VTRIP3
V3MON Trip Point Voltage X80130 X80131 X80132 X80133 X80134
2.95 2.20 2.20 2.20 0.85
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Electrical Specifications
SYMBOL VTRIP4 (Standard Settings) Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS MIN 0.85 X80130 X80131 X80132 X80133 X80134 VREF Voltage Reference Long Term Drift 10 years 2.20 0.85 1.65 0.85 0.85 0 2.25 0.90 1.70 0.90 0.90 TYP MAX 3.5 2.30 0.95 1.75 0.95 0.95 100 UNIT V V V V V V mV
PARAMETER V4MON Trip Point Voltage
AC CHARACTERISTICS tMR (Note 3) Minimum time high for reset valid on the MR pin 5 1.6 45 50 50 55 s s ms ns
tMRE (Note 3) Delay from MR enable to V1GDO LOW tDPOR (Note 3) tTO (Note 3) Device Delay before Gate assertion ViGDO turn off time
Electrical Specifications
SYMBOL tSPOR
(Programmable Parameters) Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER Delay before RESET assertion TPOR1 = 0 TPOR1 = 0 TPOR1 = 1 TPOR1 = 1 TPOR0 = 0 TPOR0 = 1 TPOR0 = 0 TPOR0 = 1
Factory Default (Note 3) (Note 3) (Note 3)
90 450 0.9 4.5
100 500 1 5
110 550 1.1 5.5
ms ms s s
tDELAYi
Time Delay used in Power Sequencing (i = 1, 3, 4) TiD1 = 0 TiD1 = 0 TiD1 = 1 TiD1 = 1 TiD0 = 0 TiD0 = 1 TiD0 = 0 TiD0 = 1 Factory Default (Note 3) (Note 3) (Note 3) 90 450 0.9 4.5 100 500 1 5 110 550 1.1 5.5 ms ms s s
Equivalent A.C. Output Load Circuit
5V 5V 5V
A.C. Test Conditions
Input pulse levels VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Standard output load
4.6k
4.6k RESET SDA 30pF
4.6k V1GDO, V3GDO, V4GDO 30pF
Input rise and fall times Input and output timing levels Output load
30pF
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Initial Power-up VCC
VREFi ViMON tDPOR tDELAYi tTO tDELAYi
ViGDO
i = 1, 3, 4
FIGURE 1. INITIAL POWER UP TIMING
MR
tMR
ViGDO tDELAYi
RESET tMRE tDELAYi + tSPOR
FIGURE 2. MANUAL RESET (MR)
MR ViMON (i= 1 to 4) tDELAY1
tDELAY1
V1GDO tDELAY3
tDELAY3 V3GDO tDELAY4 V4GDO tSPOR RESET
Any ViGDO (1st occurance)
tDELAY4 tSPOR
FIGURE 3. ViGDO, RESET TIMINGS
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Serial Interface Over the recommended operating conditions unless otherwise specified.
SYMBOL DC CHARACTERISTICS ICC1 Active Supply Current (VCC) Read or Write to Memory or CRs Input Leakage Current (SCL, WP, A0, A1) Output Leakage Current (SDA) Input LOW Voltage (SDA, SCL, WP, A0, A1) Input HIGH Voltage (SDA, SCL, WP, A0, A1) Schmitt Trigger Input Hysteresis VCC related level Fixed input level VOL Output LOW Voltage (SDA) IOL = 4.0mA 0.05 x 5 0.2 0.4 V V V VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz VIL = GND to VCC VSDA = GND to VCC Device is in Standby -0.5 VCC x 0.7 2.5 mA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILI ILO VIL VIH VHYS
15 15 VCC x 0.3 5.5
A A V V
AC CHARACTERISTICS fSCL tIN SCL Clock Frequency Pulse width Suppression Time at inputs 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb 20 +.1Cb 0.6 0 0.6 0 0.6 400 5 10 300 300 1.5 400 kHz ns s s s s s s ns s s ns ns ns s s s s s pF ms
tAA (Note 1) SCL LOW to SDA Data Out Valid tBUF (Note 1) tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO Time the bus is free before start of new transmission Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time
tDH (Note 1) Data Output Hold Time tR (Note 1) tF (Note 1) tSU:WP tHD:WP tSU:ADR tHD:ADR tSU:VP Cb (Note 3) SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time A0, A1 Setup Time A0, A1 Hold Time VP Setup Time Capacitive load for each bus line
tWC (Note 2) EEPROM Write Cycle Time NOTES: 1. This parameter is based on characterization data.
2. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. This parameter is not 100% tested.
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X80130, X80131, X80132, X80133, X80134 Timing Diagrams
tBUF
tF
tHIGH
tLOW
tR tBUF
SCL tSU:STA tHD:STA SDA IN tAA SDA OUT tDH tHD:DAT tSU:DAT tHD:DAT tSU:STO tHD:STO
FIGURE 4. BUS TIMING
START SCL
STOP Clk 1 Slave Address Byte Clk 9
SDA IN tSU:WP WP tSU:ADR A1, A0 tSU:VP tWC tHD:ADR tHD:WP
VP
FIGURE 5. WP, A0, A1, VP PIN TIMING
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
FIGURE 6. WRITE CYCLE TIMING
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X80130, X80131, X80132, X80133, X80134 Symbol Table
WAVEFORM INPUTS
Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed
Pinout
OUTPUTS
Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known
V4GDO V4MON V3GDO V3MON DNC 1 2 3 4 5 6 7 8 9 10 A1 (5mm x 5mm)
QFN package (Top view)
VCC VSS NC A0 MR 15 14 13 12 11
20 19 18 17 16 WP RESET V1GDO V1MON SCL
VCC
DNC
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 NAME V4GDO V4MON V3GDO V3MON DNC VP VCC DNC A1 SDA DESCRIPTION V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than VREF4 and goes LOW when V4MON is greater than VREF4. There is user selectable delay circuitry on this pin. V4 Voltage Monitor Input. Third voltage monitor pin. If unused connect to VCC. V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than VREF3 and goes LOW when V3MON is greater than VREF3. There is user selectable delay circuitry on this pin. V3 Voltage Monitor Input. Second voltage monitor pin. If unused connect to VCC. Do Not Connect. EEPROM programming Voltage. Connect to VCC. Do Not Connect. Address Select Input. It has an internal pull-down resistor. (>10M typical) The A0 and A1 bits allow for up to 4 X80130 devices to be used on the same SMBus serial interface. Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Serial Clock. The Serial Clock controls the serial bus timing for data input and output. V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to VCC. V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than VREF1 and goes LOW when V1MON is greater than VREF1. There is user selectable delay circuitry on this pin. RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive and the power sequencing is complete. This pin will be released after a programmable delay. Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the device. It has an internal pull-down resistor. (>10M typical) Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5secs. It has an internal pull-down resistor. (>10M typical) Ground Input. No Connect. No internal connections. Address Select Input. It has an internal pull-down resistor. (>10M typical) The A0 and A1 bits allow for up to 4 X80130 devices to be used on the same SMBus serial interface. Supply Voltage.
11 12 13 14 15 16 17 18 19 20
SCL V1MON V1GDO RESET WP MR VSS NC A0 VCC
8
SDA
VP
FN8152.0 January 20, 2005
X80130, X80131, X80132, X80133, X80134 Description
The X80130 is a voltage supervisor/sequencer with three built in voltage monitors. This allows the designer to monitor up to three voltages and sequence up to four events. Low voltage detection circuitry protects the system from power supply failure or "brown out" conditions, resetting the system and resequencing the voltages when any of the monitored inputs fall below the minimum threshold level. The RESET pin is active until all monitored voltages reach proper operating levels and stabilize for a selectable period of time. Five common low voltage combinations are available, however, Intersil's unique circuits allow the any voltage monitor threshold to be reprogrammed for special needs or for applications requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. Activating the manual reset both controls the RESET output and resequences the supplies through control of the ViGDO pins. The X80130 has 2kb of EEPROM for system configuration, manufacturing or maintenance information. This memory is protected to prevent inadvertent changes to the contents.
TPOR1 0 0 1 1 TABLE 1. POR RESET DELAY OPTIONS TPOR0 0 1 0 1 tSPOR DELAY BEFORE RESET ASSERTION 100 miliseconds (default) 500 miliseconds 1 second 5 seconds
Manual Reset
The manual reset option allows a hardware reset of the power sequencing pins. These can be used to recover the system in the event of an abnormal operating condition. Activating the MR pin for more than 5s sets all of the ViGDO outputs and the RESET output active (LOW). When MR is released (and if all supplies are still at their proper operating voltage) then the ViGDO and RESET pins will be released after their programmed delay periods.
Triple Voltage Monitoring
X80130 monitors 3 voltage inputs. When the ViMON (i =1, 3, 4) input is detected to be above the input threshold, the output ViGDO (i =1, 3, 4) goes inactive (LOW). The ViGDO signal is de-asserted after a delay of 100ms. This delay can be changed on each ViGDO output individually with bits in register CR3. The delay can be 100ms, 500ms, 1s and 5s. Each ViGDO signal remains active until its associated ViMON input rises above the threshold.
TABLE 2. ViGDO OUTPUT TIME DELAY OPTIONS TiD1 0 0 1 1 TiD0 0 1 0 1 tDELAYi 100ms (default) 500ms 1 secs 5 secs
Functional Description
Power On Reset and System Reset With Delay
Application of power to the X80130 activates a Power On Reset circuit that pulls the RESET pin active. This signal, if used, prevents the system microprocessor from starting to operate while there is insufficient voltage on any of the supplies. This circuit also does the following: * It prevents the processor from operating prior to stabilization of the oscillator. * It allows time for an FPGA to download its configuration prior to initialization of the circuit. * It prevents communication to the EEPROM during unstable power conditions, greatly reducing the likelihood of data corruption on power up. * It allows time for all supplies to turn on and stabilize prior to system initialization. The POR/RESET circuit is activated when all voltages are within specified ranges and the V1GDO, V3GDO, and V4GDO time-out conditions are met. The POR/RESET circuit will then wait tSPOR and de-assert the RESET pin. The POR delay may be changed by setting the TPOR bits in register CR2. The delay can be set to 100ms, 500ms, 1 second, or 5 seconds.
where i is the specific voltage monitor (i = 1, 3, 4).
Fault Detection
The X80130 contains a Fault Detection Register (FDR) that provides the user the status of the causes for a RESET pin active (See Table 20). At power-up, the FDR is defaulted to all "0". The system needs to initialize the register to 0Dh before the actual monitoring can take place. In the event that any one of the monitored sources fail, the corresponding bit in the register changes from a "1" to a "0" to indicate the failure. When a RESET is detected by the main controller, the controller should read the FDR and note the cause of the fault. After reading the register, the controller can reset the register bit back to all "1" in preparation for future failure conditions.
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Flexible Power Sequencing of Multiple Power Supplies
The X80130 provides several circuits such as multiple voltage monitors, programmable delays, and output drive signals that can be used to set up flexible power monitoring or sequencing schemes system power supplies. Below are two examples: 1. Power Up of Supplies In Parallel Using Programmable Delays (See Figure 7 and Figure 8). The X80130 monitors several power supplies, powered by the same source voltage, that all begin power up at the same time. Each voltage source is fed into the ViMON inputs to the X80130. The ViMON inputs monitor the voltage to make sure it has reached the minimum desired level. When each voltage monitor determines that its input is good, a counter starts. After the programmed delay time, the X80130 sets the ViGDO signals LOW. The ViGDO signals can be wire ORed together and tied to an interrupt on the microcontroller. Any individual voltage failure can be viewed in the Fault Detection Register. In the factory default condition, each ViGDO output is instructed to go LOW 100ms after the input voltage reaches its threshold. However, each ViGDO delay is individually selectable as 100ms, 500ms, 1s and 5s. The delay times are charged via the SMBus during calibration of the system.
Power Supplies 5V 3.3V 2.5V 1.2V
2. Power Up of Supplies Via Relay Sequencing Using Voltage Monitors (See Figure 9 and Figure 10). Several power supplies and their respective power up start times can be controlled using the X80130 such that each of the power supplies will start in a relay sequencing fashion. In the following example, the 1st supply is allowed to power up when the input regulated supply reaches an acceptable threshold. Subsequent supplies power up after the prior supply has reached its operating voltage. This configuration ensures that each subsequent power supply turns on after the preceding supplies voltage output is valid. Again, the X80130 offers programmable delays for each voltage monitor and this delay is selectable via the SMBus during calibration of the system.
V1MON Programmable Delay
Can Choose Different Delays for each Voltage Monitor
tDELAY1 V1GDO
100ms 500ms 1sec 5secs
V3MON tDELAY3 V3GDO Programmable Delay
On/Off On/Off On/Off
V4MON tDELAY4 V4GDO Programmable Delay
tSPOR C X80130/31/32/33/34 V4GDO V4MON V3GDO V3MON V1GDO V1MON RESET MR VCC1 IRQ RESET VCC2 FPGA VCC1 VCC2 ASIC VCC1 VCC2 RESET Timing not to scale
Programmable Delay
FIGURE 8. PARALLEL POWER CONTROL - TIMING
FIGURE 7. EXAMPLE APPLICATION OF PARALLEL POWER CONTROL
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12V
Power 5V Supply On/Off 1.2V Power Supply On/Off Power 3.3V Supply On/Off
VCC1
C
VCC2 RESET FPGA
VCC1 VCC2
X80140/41/42/43 VCC1 VCC2 VCC V4GDO V4MON V3GDO V3MON V1MON V1GDO 5V RESET MR
ASIC
FIGURE 9. EXAMPLE OF RELAY POWER SUPPLY SEQUENCING
V1MON (12V) tDELAY1
V1MON threshold Programmable Delay
100ms 500ms 1sec 5sec
Timing Not To Scale Example: Four Independent Power Supplies in relay timing
V1GDO Power Supply #2 OUTPUT (5V) tDELAY3 V3GDO Power Supply #3 OUTPUT (1.2V)
Power Supply #2 ON V2MON threshold Programmable Delay 100ms 500ms 1sec 5sec
Power Supply #3 ON V3MON threshold tDELAY4 Programmable Delay 100ms 500ms 1sec 5sec
V4GDO Power Supply #4 OUTPUT (3.3V)
Power Supply #4 ON
tSPOR RESET
FIGURE 10. RELAY SEQUENCING OF DC-DC SUPPLIES (TIMING)
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X80130, X80131, X80132, X80133, X80134 Control Registers and Memory
The user addressable internal control, status and memory components of the X80130 can be split up into three parts: * Control Register (CR) * Fault Detection Register (FDR) * EEPROM array X80130. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Note, a write to FDR or RSR does not require that WEL=1.
Registers
The Control Registers and Fault Detection Register are summarized in Table 4. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The values of the Register Block can be read at any time by performing a random read (See Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation. The X80130 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory.
BP1 and BP0: Block Protect Bits
The Block Protect Bits, BP1 and BP0, determine which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array.
PROTECTED ADDRESSES (SIZE) None (Default) C0h - FFh (64 bytes) 80h - FFh (128 bytes) 00h - FFh (256 bytes) BP1 BP0
ARRAY LOCK None (Default) Upper 1/4 Upper 1/2 All
0 0 1 1
0 1 0 1
WPEN: Write Protect Enable
The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2 and CR3) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that are not block protected can be written.
Register and Memory Protection
In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80130. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin.
Non Volatile Programming Voltage (VP)
Nonvolatile writes require that a programming voltage be applied to the VP for the duration of a nonvolatile write operation.
WEL: Write Enable Latch
A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the
TABLE 3. WRITE PROTECT CONDITIONS MEMORY ARRAY NOT BLOCK PROTECTED Writes Blocked Writes Enabled Writes Enabled Writes Enabled MEMORY ARRAY BLOCK PROTECTED Writes Blocked Writes Blocked Writes Blocked Writes Blocked WRITES TO CR1, CR2, CR3 Writes Blocked Writes Enabled Writes Enabled Writes Blocked
WEL LOW HIGH HIGH HIGH
WP X LOW X HIGH
WPEN X X LOW HIGH
PROTECTION Hardware Software Software Hardware
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TABLE 4. REGISTER ADDRESS MAP BYTE ADDR. 00H 01H 02H 03H FF BIT NAME CR0 CR1 CR2 CR3 FDR CONTROI/STATUS Write Enable EEPROM Block Control POR Timing ViGDO TIme Delay Fault Detection Register 7 WEL WPEN 0 T4D1 0 6 0 0 0 T4D0 0 5 0 0 0 T3D1 0 4 0 BP1 0 T3D0 0 3 0 BP0 TPOR1 0 V40S 2 0 0 TPOR0 0 V30S 1 0 0 0 T1D1 0 0 0 0 0 T1D0 V10S MEMORY TYPE Volatile EEPROM EEPROM EEPROM Volatile
TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY OPERATION CONTROL /STATUS LOCATION(S) REGISTER BITS DESCRIPTION (SEE FUNCTIONAL FOR DETAILS)
SOFTWARE CONTROL BITS EEPROM Write Enable EEPROM Write Protect EEPROM Block Protect WEL WPEN BP1 BP0 CR0 CR1 CR1 7 7 4:3 WEL = 1 enables write operations to the control registers and EEPROM. WEL = 0 prevents write operations. WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and the EEPROM. BP1=0, BP0=0 : No EEPROM memory protected. BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected. BP1=1, BP0=1 : All of EEPROM memory protected. TPOR1=0, TPOR0=0 : RESET delay = 100ms TPOR1=0, TPOR0=1 : RESET delay = 500ms TPOR1=1, TPOR0=0 : RESET delay = 1s TPOR1=1, TPOR0=1 : RESET delay = 5s TiD1=0, TiD0=0 : ViGDO delay = 100ms TiD1=0, TiD0=1 : ViGDO delay = 500ms TiD1=1, TiD0=0 : ViGDO delay = 1s TiD1=1, TiD0=1 : ViGDO delay = 5s
RESET Time Delay
TPOR0 TPOR1
CR2
3:2
V1GDO Time Delay V3GDO Time Delay V4GDO Time Delay STATUS BITS 1st Voltage Monitor 3rd Voltage Monitor 4th Voltage Monitor
T1D0 T1D1 T3D0 T3D1 T4D0 T4D1
CR3 CR3 CR3
1:0 5:4 7:6
V1OS V3OS V4OS
FDR FDR FDR
0 2 3
V1OS = 0 : V1GDO pin has been asserted (must be preset to 1). V3OS = 0 : V3GDO pin has been asserted (must be preset to 1). V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).
Bus Interface Information
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a STOP condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a STOP condition.
Serial Clock and Data
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 11).
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The
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device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. On power up, the SCL pin must be brought LOW prior to the START condition.
SCL from Master Data Output from Transmitter Data Output from Receiver Start
1
8
9
Serial Stop Condition
All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA when SCL is HIGH, followed by a HIGH to LOW on SCL. After going LOW, SCL can stay LOW or return HIGH. The STOP condition also places the device into the Standby power mode after a read sequence.
Acknowledge
FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (See Figure 12). The device will respond with an acknowledge after recognition of a START condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. The device does not acknowledge any instructions following a non-volatile write operation, unless the VP pin has the recommended programming voltage applied for the duration of the write cycle. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a STOP condition to return the device to Standby mode and place the device into a known state.
Device Addressing
Addressing Protocol Overview
Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being clocked into the SMBus port on the SCL and SDA pins. The Slave address selects the part of the device to be addressed, and specifies if a Read or Write operation is to be performed.
Slave Address Byte
Following a START condition, the master must output a Slave Address Byte. This byte consists of three parts: * The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier MUST be set to 1010 in order to select the device. * The next two bits (SA3 - SA2) are slave address bits. The bits received via the SMBus are compared to A0 and A1 pins and must match or the communication is aborted. The next bit, SA1, selects the device memory sector. There are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers. * The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed. When the R/W bit is "1", then a READ operation is selected. A "0" selects a WRITE operation (Refer to Figure 13).
SCL
SDA
Start
Stop
FIGURE 11. VALID START AND STOP CONDITIONS
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PAGE WRITE
External Device Address SA3 SA2 Memory READ / Select WRITE
Device Type Identifier
SA7
SA6
SA5
SA4 0
SA1 MS
SA0 R/W
1
0
1
A1
A0
INTERNAL ADDRESS (SA1) 0 1
INTERNALLY ADDRESSED DEVICE EEPROM Array Control Register, Fault Detection Register
The device is capable of a page write operation (See Figure 14). It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page (See Figure 15). This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a STOP condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. STOPS AND WRITE MODES Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a STOP is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be affected. ACKNOWLEDGE POLLING The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the STOP condition is issued to indicate the end of the master's byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a START condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation (See Figure 18).
BIT SA0 0 1
OPERATION WRITE READ
FIGURE 13. SLAVE ADDRESS FORMAT
Serial Write Operations
Before any write operations can be performed, a programming supply voltage (VP) must be supplied. This voltage is only needed for programming, but the nonvolatile registers and EEPROM locations cannot be programmed without it. In order to successfully complete a write operation to either a Control Register or the EEPROM array, the Write Enable Latch (WEL) bit must first be set and either the WP pin or the WPEN bit must be LOW. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the STOP condition. BYTE WRITE For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a STOP condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. A write to a protected block of memory will suppress the acknowledge bit. 15
FN8152.0 January 20, 2005
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(1 to n to 16) Signals from the Master S t a r t Slave Address Byte Address Data (1) Data (n) S t o p
SDA Bus
1010
Signals from the Slave
0 A C K A C K A C K A C K
FIGURE 14. PAGE WRITE OPERATION
7 Bytes
5 Bytes
address =6
address pointer ends here Addr = 7
address 10
address n-1
FIGURE 15. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10
Signals from the Master
S t a r t
Slave Address
Byte Address
S t a r t
Slave Address
S t o p 1 A C K
SDA Bus
1010
0 A C K A C K
1010
Signals from the Slave
Data
FIGURE 16. RANDOM ADDRESS READ SEQUENCE
Signals from the Master
S t a r t
Slave Address
S t o p
SDA Bus
1010
1 A C K
Signals from the Slave
Data
FIGURE 17. CURRENT ADDRESS READ SEQUENCE
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CURRENT ADDRESS READ
Byte Load Completed by Issuing STOP. Enter ACK Polling
Issue START
Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a STOP condition (See Figure 17 or the address, acknowledge, and data transfer sequence).
Issue Slave Address Byte (Read or Write)
Issue STOP
NO ACK Returned?
YES
Operational Notes
The device powers-up in the following state: * The device is in the low power standby state. * The WEL bit is set to `0'. In this state it is not possible to write to the device. * SDA pin is the input mode.
High Voltage Cycle Complete. Continue Command Sequence? NO
Issue STOP
YES Continue Normal Read or Write Command Sequence
Data Protection
The following circuitry has been included to prevent inadvertent writes: * The WEL bit must be set to allow write operations. * The proper clock count and bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle. * The WP pin, when held HIGH, prevents all writes to the array and all the Register. * A programming voltage must be applied to the VP pin prior to any programming sequence.
PROCEED
FIGURE 18. ACKNOWLEDGE POLLING SEQUENCE
Serial Read Operations
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. RANDOM READ Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the START condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another START condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a STOP condition (See Figure 16 for the address, acknowledge, and data transfer sequence).
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X80130, X80131, X80132, X80133, X80134 Packaging Information
20-Lead Quad Flat No Lead Package (Package Code: Q20) 5mm x 5mm Body with 0.65mm Lead Pitch
C
Pin 1 Indent
A3 A1
b
E
E2
e
D2
D
L
A yC
DIMENSIONS IN MILLIMETERS SYMBOLS A A1 b A3 D D2 E E2 e L y MIN 0.70 0.00 0.25 0.19 4.90 3.70 4.90 3.70 -- 0.35 NOM 0.75 0.02 0.30 0.20 5.00 3.80 5.00 3.80 0.65 0.40 -- MAX 0.80 0.05 0.35 0.25 5.10 3.90 5.10 3.90 -- 0.45 0.08
Note:
1. The package outline drawing is compatible with JEDEC MO-220; variations: WHHC-2, except dimensions D2 and E2. 2. The terminal #1 identifier is a laser marked feature
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN8152.0 January 20, 2005

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